This present invention relates to digital interface circuitry. More specifically, it relates to on-die termination (ODT) circuitry.
Computer systems and other electronic systems typically use buses for interconnecting integrated circuit components so that the integrated circuit components can communicate with one another. System buses typically connect master devices, such as microprocessors and controllers, and slave devices, such as memories and bus transceivers.
Each master and slave device that is coupled to the bus typically includes output driver circuitry for driving signals onto the bus. Prior bus systems have employed a variety of types of logic circuitry including: transistor-transistor logic (xe2x80x9cTTLxe2x80x9d), emitter-coupled logical (xe2x80x9cECLxe2x80x9d), complementary-metal-oxide-semiconductor (CMOS), N-channel metal oxide semiconductor (xe2x80x9cNMOSxe2x80x9d), P-channel metal oxide semiconductor (xe2x80x9cPMOSxe2x80x9d), and gunning transistor logic (xe2x80x9cGTLxe2x80x9d).
The different types of logic circuitry described above are generally driven by voltage level signals. For example, a logic-1 in TTL is typically represented by a voltage signal level of 5V while a logic-0 is typically represented by a voltage signal level of 0V. As supply voltage levels for digital circuits have steadily declined from 5V to approximately 1.8V, it has become advantageous, to provide buses that are driven by a current mode output driver. One benefit to a current mode driver is a reduction of peak switching current. For a voltage mode driver the output transistor of the driver must be sized to drive the maximum specified current under worst case operating conditions. Under nominal conditions with less than maximum load, the current transient when the output is switched, but before it reaches the rail, can be very large. The current mode driver, on the other hand, draws a known current regardless of load and operating conditions.
In addition, for a voltage mode driver, impedance discontinuities occur when the driving device is characterized by a low output impedance when in a sending state. These discontinuities cause reflections which dictate extra bus settling time. Current mode drivers, however, are characterized by a high output impedance so that a signal propagating on the bus encounters no significant discontinuity in line impedance due to a driver in a sending state. Thus, reflections are typically avoided and the required bus settling time is decreased.
An example of a current mode bus is disclosed in U.S. Pat. No. 4,481,625, issued Nov. 6, 1984, entitled High Speed Data Bus System. An NMOS current mode driver for a low voltage swing bus is disclosed in PCT international patent application number PCT/US91/02590 filed Apr. 16, 1991, published Oct. 31, 1991, and entitled Integrated Circuit I/O Using a High Performance Bus Interface.
One disadvantage of certain prior current mode drivers is that current sometimes varies from driver to driver. Variations can also happen over time. Temperature variations, process variations, and power supply variations sometimes cause such variations. Current variations in turn lead to voltage level variations on the bus. Bus voltage level variations can in turn lead to the erroneous reading of bus levels, which can result in the loss of data or other errors. In addition, attempts to design around these variations by raising voltage levels sometimes leads to higher power dissipations, especially in extreme cases. In any event, variations in bus voltage levels are typically more problematic for buses with low voltage swings.
FIG. 1 is a functional block diagram illustrating an example of a bus system 10. In this example, a bus 20 provides for data transfer between a memory controller device 30, which is the bus master for bus 20, and RDRAMs 12 and 14, which are slave devices on bus 20. Bus 20 is a high speed, low voltage swing bus that typically includes a plurality of transmission lines for carrying data and control information. Each of memory controller 30 and RDRAMs 12 and 14 typically includes an interface circuit for coupling to bus 20, such as interface driver circuit 32 for memory controller 30. Each interface circuit typically includes a plurality of current mode drivers for driving each line of bus 20, e.g. for each master and slave device, there is one output driver for each transmission line of bus 20. Each of the current mode drivers accurately provides a desired current for the respective line of bus 30.
Each of the current mode drivers typically includes a plurality of transistors coupled in parallel between a respective transmission line of the bus and a ground voltage supply rail. A logic circuit is coupled to the gates of the plurality of transistors. The widths of the transistors are typically binary multiples of one another. A current controller is coupled to the logic circuit for controlling the logic circuit in order to turn on or off a particular combination of the plurality of transistors such that a desired current draw for the line of the bus may be selected. The desired current for the line of the bus, in turn, becomes a desired voltage for the line of bus 20. The controller typically includes a variable level circuit, a comparator, a counter, and a control logic. Once selected, the desired current is relatively independent of power supply, process, and temperature variations. U.S. Pat. No. 5,254,883 to Horowitz et al. for Electrical Current Source Circuitry for a Bus, herein incorporated by reference in its entirety for all purposes, illustrates an example of a circuit for setting a desired current draw for circuitry interfacing with a bus as well as information regarding typical bus systems such as bus system 10.
As noted above, the modern trend for the interface drivers for bus 20 is to use current mode drivers having low voltage swing signals. The current mode drivers of interface driver 32 of memory controller 30 and RDRAMs 12 and 14 control the voltage levels of bus 20. When a current mode driver is in an xe2x80x9coffxe2x80x9d state, then the respective bus line will either stay at a high voltage level or rise to the high voltage level. When the current mode driver is in an xe2x80x9coffxe2x80x9d state, there is approximately zero voltage drop across the line termination resistors, represented in FIG. 1 by resistor 26, because the current mode driver is not drawing current from the bus line. Thus, the voltage level of the bus line will rise to the termination voltage Vterm for bus 20.
When a current mode driver is in an xe2x80x9conxe2x80x9d state, then the current mode driver draws current from the respective bus line and lowers the voltage level of the bus line. In other words, when the current mode driver is in an xe2x80x9conxe2x80x9d state, pull down current flows through the current driver to the ground supply rail. The low voltage level of bus 20 is, accordingly, determined by the pull down current drawn by the driver. The pull down current flows through the termination resistor 26 causing a voltage drop to appear on the respective line of bus 20. The pull down current (flowing through the output driver and the respective termination resistor) is referred to as the desired current. The magnitude of the desired current can be set or selected by the user to allow for different bus impedance, noise immunity, and power dissipation requirements.
FIG. 5 is a voltage waveform diagram illustrating how the current adjustment performed by the circuits of FIGS. 2 and 4, discussed below, can affect the signal waveform generated by an output driver. In FIG. 5, waveform 180 illustrates a response where an output high voltage level VOH starts at VTERM (typically 1.8 V in many current RAMBUS designs) and is pulled low by the output driver to an output low voltage level VOL (typically 1.0 V in many current RAMBUS designs). At the output high voltage level VOH, the output driver circuit draws no current. At the output low voltage level VOL, the output driver draws sufficient current to pull the bus line to 1.0V, in this example. When the output current is properly adjusted, then the output voltage swings equally above and below an externally provided reference voltage VREF, which is typically 1.4V in current RAMBUS designs. However, if the current draw is insufficient, then curve 184 may occur, where the output voltage does not quite reach the output low voltage level VOL. Conversely, if the current draw is excessive, then curve 182 may occur, where the output low voltage level VOL may be exceeded.
In addition to adjusting the desired pull down current for the drivers, it is important to have the appropriate impedance for the driver. The signals driven onto the bus lines of bus 20 are reflected from other interfaces on the bus. For example, when RDRAM 12 transmits onto bus 20, a 400 mV signal is transmitted towards memory controller 30 on bus segment 24 and towards RDRAM 14 on bus segment 22. Because of the high operating speeds of modem bus systems, bus segments 22 and 24 are illustrated here as transmission lines that require time for a signal to traverse. When the signal from RDRAM 12 encounters the termination of interface driver 32 on bus 20, then a portion of the signal is reflected and results in an 800 mV signal, in this example, that is reflected back towards RDRAM 12. An appropriate terminating impedance in driver 32 is important in order to limit the amplitude of the reflected signal. Also, terminating resistor 26 is an external device and typically has a value of approximately 28xcexa9 or 56xcexa9, which will affect the function of the driver circuits.
FIG. 2 is a functional block diagram that illustrates one example of the current control circuitry present in the interface driver 32 of memory controller 30 and the RDRAM 14 of FIG. 1. In interface driver 32, a voltage drop caused by current drawn by current source 134 coupled in series with external resistor 110 and VTERM is compared to a reference voltage VREF by comparator 120 to generate an UP/DOWN signal. Counter 130 maintains a current control signal CCS1, that is incremented or decremented responsive to the value of the UP/DOWN signal and a clock signal K1. The current control signal CCS1 drives current sources 134 and 136. Current source 134 provides a feedback loop to comparator 120. Current source 136 provides a controlled current draw from data input line IND coupled to bus 20. Likewise, RDRAM 14 includes a counter 140 for producing another current control value CCS2 that controls the current in current source 142 to obtain a current draw from INW coupled to bus 20.
The current drawn by current source 134 will increase until the voltage at both input terminals of comparator 120 is approximately the same. This condition will typically result in the UP/DOWN signal oscillating back and forth as the value of CCS1 adjusts the current flow through current source 134 and the current flow is fed back through comparator 120.
FIG. 3 is a circuit diagram illustrating one example of the implementation for current sources 134 and 136. Here, current control signal CCS1 is composed of six signal lines and current source 136 is implemented as a plurality of NMOS transistors, each signal line of CCS1 driving the gate of one of the transistors. In one approach, each of the transistors is sized proportional to the significance of the bit line of CCS1 that drives it. For example, the transistor driven by CCS1(0), the least significant bit of CCS1, is of a unit size (e.g. the smallest transistor achievable through the fabrication process for the overall circuit), while the transistors driven by CCS1(1) and CCS1(2), the next two most significant bit lines, are twice and four times the unit size, respectively. Other approaches to implementing the current sources are also possible and well understood within the art.
FIG. 4 is a functional block diagram that illustrates another approach to generating a current control signal CCS suitable for controlling the current draw of the interface drivers for an on-die termination (ODT). The circuit 150 of FIG. 4 is configured to improve the output swing of the driver circuit by controlling the current relative to both the output low voltage level VOL and the output high voltage level VOH, which may obtained by sampling the two logic states as output by the driver. The output low voltage level VOL is coupled to the output high voltage level VOH through resistors 152 and 154, which have a resistance on the order of 5Kxcexa9. A sampling voltage VS is obtained at the node where resistors 152 and 154 are coupled. The sampling voltage VS is compared to the reference voltage VREF by comparator 160 and the output of the comparator is latched by latch 164 under the control of a CCEVAL signal to obtain an UP/DOWN control signal for counter 170.
The voltage level signals VOL and VOH may be obtained during a training sequence for the output driver that is coordinated with the CCEVAL signal, which may, for example, take place as part of a refresh cycle for the RDRAMs 12 and 14 or as part of a power-up cycle. FIG. 4 reflects the approach taken in U.S. Pat. No. 6,094,075 to Garrett, Jr. et al., herein incorporated by reference in its entirety for all purposes. However, any error in the value of resistors 152 and 154 tends to be doubled due to nature of the resistive divider in the design.
The present invention involves a circuit and method for interfacing to a bus line. The present invention derives an output low reference voltage from an external terminating voltage and an external reference voltage corresponding to the middle of a logic voltage range for the bus line. A feedback loop is used to compare a voltage at the pad to the output low reference voltage. An on-die termination current sourced to the pad is adjusted accordingly. This allows the present invention to adapt to a variety of external termination resistance values. Further, the output low reference voltage is utilized to generate a reference current sourced to an output amplifier, which causes the output swing of the amplifier to track along with the external terminating voltage and the external reference voltage. In another aspect of the present invention, an alternating pattern of logic high and logic low voltage values is transmitted at the pad and received. The received data pattern is compared to the transmitted data pattern to adjust the on-die termination current and the reference current.
One embodiment of a bus interface driver circuit, according to the present invention, includes an external termination pad configured to be coupled to a bus line, the bus line having a termination voltage and a termination impedance, and a first comparator circuit configured to compare the termination voltage to a first reference voltage in order to generate a second reference voltage. A first current source circuit is configured to receive the second reference voltage and generate a reference current that corresponds to the second reference voltage. A driver circuit is configured to receive the reference current and a data signal, where the driver circuit is configured to modulate the reference current responsive to the data signal in order to generate an output current at the external termination pad. A second comparator circuit is configured to compare the termination voltage to the first reference voltage in order to generate a third reference voltage and further compare the third reference voltage to an output voltage at the external termination pad in order to generate a current control signal. Finally, a second current source is configured to receive the current control signal and generate an on-die termination current corresponding to the current control signal at the external termination pad. Another aspect of this embodiment of the present invention involves a transmit pipeline circuit configured to transmit a predetermined data pattern at the external termination pad responsive to a transmit clock signal, the predetermined data pattern alternating between high and low logic voltage levels. This aspect of the present invention also includes a receive pipeline configured to receive, responsive to a receive clock signal, a data pattern at the external termination pad corresponding to the predetermined data pattern transmitted by the transmit pipeline circuit. This aspect of the present invention further includes a comparator configured to compare the received data pattern to the predetermined data pattern in order to generate a counter control signal configured to increase and decrease the current control signal according to the comparison between the received data pattern and the predetermined data pattern.
An embodiment of a method, according to the present invention, for interfacing to a bus calls for providing an external termination pad configured to be coupled to a bus line and tracking a difference between a terminating voltage for the bus and a first reference voltage for the bus to produce a second reference voltage. The method further sets forth generating a reference current that corresponds to the second reference voltage and sourcing the reference current to an amplifier. The method also calls for amplifying a data signal with the amplifier to drive the external termination pad and generating a current control signal by comparing a voltage at the external termination pad to the second reference voltage. Finally, the method recites sourcing an on-die termination current to the external termination pad that corresponds to the current control signal.
An embodiment of a bus system, according to the present invention, includes at least one bus line, a termination voltage terminal coupled to the bus line and configured to have an external termination voltage, and a termination resistor coupled between the termination voltage terminal and the bus line and having an external resistance value. The bus system also includes a bus interface device having an external termination pad coupled to the bus line. The bus interface device is configured to receive the termination voltage and an external reference voltage and compare the termination voltage and an external reference voltage in order to generate an output low reference voltage. The device is further configured to compare the output low reference voltage to a voltage at the external termination pad in order to generate a current control signal, where the device includes a current source configured to source current to the external termination pad responsive to the current control signal. In another aspect of this embodiment of the present invention, the bus interface device is further configured to generate a reference current corresponding to the output low reference voltage and the device further includes an amplifier for generating an output signal at the external termination pad responsive to a data signal, where the amplifier operates from the reference current such that an output swing of the output signal of the amplifier corresponds to the output low reference voltage. In still another aspect of this embodiment of the present invention, the bus interface device is further configured to generate the current control signal by transmitting a predetermined data pattern at the external termination pad, where the predetermined data pattern alternates between high and low logic levels, compare a signal present at the external termination pad to the output low reference voltage in order to obtain a received data pattern that corresponds to the transmitted predetermined data pattern, and compare the received data pattern to the predetermined data pattern in order to adjust the current control signal.
The foregoing and other features and advantages of the circuit and method for interfacing with a bus line will be apparent from the following more particular description of exemplary embodiments of the present invention as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views.